Important update on essential technology for hyperscale AI that enhances performance, functionality, and reinforces security.
Improvements in performance and security are a priority in this recent update of CXL.
The CXL 3.2 specification has been announced by the CXL Consortium, introducing a series of significant improvements for this technology. Among the major advancements highlighted are the optimization of monitoring and management of CXL memory devices, which will benefit both operating systems and applications.
A crucial aspect of this update is the focus on security, incorporating the Trusted Security Protocol (TSP). CXL is essential in the interaction between GPUs and CPUs with memory, facilitating communication between devices and reducing latencies, which contributes to faster and more efficient performance in processing large volumes of data.
Given the rise of generative artificial intelligence, the importance of CXL has grown due to the rapid data processing demands. This new version of the specification delves into improvements in monitoring and managing CXL memory devices. A CXL Hot Page Monitoring Unit (CHMU) has been included, specifically designed to optimize the memory hierarchy.
Additionally, compatibility with PCIe management message passing (MMPT) and improvements in CXL online firmware have been announced. Security updates focus on the TSP, which includes new features for metadata storage, expansion of IDE protection, and enhanced compliance testing for interoperability.
The consortium also ensured full backward compatibility with previous CXL specifications. According to Larrie Carr, president of the CXL Consortium, this new specification represents a significant advancement for the CXL ecosystem, focusing on improvements in security, compliance, and functionality of CXL memory devices, while promoting an open interconnect and an interoperable ecosystem for heterogeneous memory and computing solutions.
